//Original:/testcases/core/c_dsp32shiftim_lhalf_ln/c_dsp32shiftim_lhalf_ln.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5)
# mach: bfin

.include "testutils.inc"
	start



// lshift : neg data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x0000c001;
imm32 r2, 0x0000c002;
imm32 r3, 0x0000c003;
imm32 r4, 0x0000c004;
imm32 r5, 0x0000c005;
imm32 r6, 0x0000c006;
imm32 r7, 0x0000c007;
R0.L = R0.L << 1;
R1.L = R1.L << 0;
R2.L = R2.L << 0;
R3.L = R3.L << 0;
R4.L = R4.L << 0;
R5.L = R5.L << 0;
R6.L = R6.L << 0;
R7.L = R7.L << 0;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x0000C001;
CHECKREG r2, 0x0000C002;
CHECKREG r3, 0x0000C003;
CHECKREG r4, 0x0000C004;
CHECKREG r5, 0x0000C005;
CHECKREG r6, 0x0000C006;
CHECKREG r7, 0x0000C007;

imm32 r0, 0x00008001;
imm32 r1, 0x00000001;
imm32 r2, 0x0000d002;
imm32 r3, 0x0000e003;
imm32 r4, 0x0000f004;
imm32 r5, 0x0000c005;
imm32 r6, 0x0000d006;
imm32 r7, 0x0000e007;
R1.L = R0.L << 1;
R2.L = R1.L << 2;
R3.L = R2.L << 3;
R4.L = R3.L << 4;
R5.L = R4.L << 5;
R6.L = R5.L << 6;
R7.L = R6.L << 7;
R0.L = R7.L << 8;
imm32 r1, 0x2000d001;
imm32 r2, 0x2000000f;
imm32 r3, 0x2000e003;
imm32 r4, 0x2000f004;
imm32 r5, 0x2200f005;
imm32 r6, 0x2000f006;
imm32 r7, 0x2000f007;
imm32 r0, 0x2000c001;

R2.L = R0.L << 10;
R3.L = R1.L << 12;
R4.L = R2.L << 13;
R5.L = R3.L << 14;
R6.L = R4.L << 15;
R7.L = R5.L << 15;
R0.L = R6.L << 2;
R1.L = R7.L << 3;
CHECKREG r0, 0x20000000;
CHECKREG r1, 0x20000000;
CHECKREG r2, 0x20000400;
CHECKREG r3, 0x20001000;
CHECKREG r4, 0x20000000;
CHECKREG r5, 0x22000000;
CHECKREG r6, 0x20000000;
CHECKREG r7, 0x20000000;

imm32 r0, 0x30009001;
imm32 r1, 0x3000a001;
imm32 r2, 0x3000b002;
imm32 r3, 0x30000010;
imm32 r4, 0x3000c004;
imm32 r5, 0x3000d005;
imm32 r6, 0x3000e006;
imm32 r7, 0x3000f007;
R3.L = R0.L << 12;
R4.L = R1.L << 13;
R5.L = R2.L << 14;
R6.L = R3.L << 15;
R7.L = R4.L << 11;
R0.L = R5.L << 12;
R1.L = R6.L << 13;
R2.L = R7.L << 15;
CHECKREG r0, 0x30000000;
CHECKREG r1, 0x30000000;
CHECKREG r2, 0x30000000;
CHECKREG r3, 0x30001000;
CHECKREG r4, 0x30002000;
CHECKREG r5, 0x30008000;
CHECKREG r6, 0x30000000;
CHECKREG r7, 0x30000000;
// RHx by RLx
imm32 r0, 0x00000040;
imm32 r1, 0x00010040;
imm32 r2, 0x00020040;
imm32 r3, 0x00030040;
imm32 r4, 0x00040040;
imm32 r5, 0x00050040;
imm32 r6, 0x00060040;
imm32 r7, 0x00070040;
R0.L = R0.H << 0;
R1.L = R1.H << 1;
R2.L = R2.H << 2;
R3.L = R3.H << 3;
R4.L = R4.H << 4;
R5.L = R5.H << 5;
R6.L = R6.H << 6;
R7.L = R7.H << 7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010002;
CHECKREG r2, 0x00020008;
CHECKREG r3, 0x00030018;
CHECKREG r4, 0x00040040;
CHECKREG r5, 0x000500A0;
CHECKREG r6, 0x00060180;
CHECKREG r7, 0x00070380;

imm32 r0, 0x90010000;
imm32 r1, 0x00010001;
imm32 r2, 0x90020000;
imm32 r3, 0x90030000;
imm32 r4, 0x90040000;
imm32 r5, 0x90050000;
imm32 r6, 0x90060000;
imm32 r7, 0x90070000;
R1.L = R0.H << 1;
R2.L = R1.H << 2;
R3.L = R2.H << 3;
R4.L = R3.H << 4;
R5.L = R4.H << 5;
R6.L = R5.H << 6;
R7.L = R6.H << 7;
R0.L = R7.H << 8;
CHECKREG r1, 0x00012002;
CHECKREG r2, 0x90020004;
CHECKREG r3, 0x90038010;
CHECKREG r4, 0x90040030;
CHECKREG r5, 0x90050080;
CHECKREG r6, 0x90060140;
CHECKREG r7, 0x90070300;
CHECKREG r0, 0x90010700;


imm32 r0, 0xa0010000;
imm32 r1, 0xa0010000;
imm32 r2, 0xa002000f;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xa0050000;
imm32 r6, 0xa0060000;
imm32 r7, 0xa0070000;
R2.L = R0.H << 15;
R3.L = R1.H << 15;
R4.L = R2.H << 15;
R5.L = R3.H << 15;
R6.L = R4.H << 15;
R7.L = R5.H << 15;
R0.L = R6.H << 15;
R1.L = R7.H << 15;
CHECKREG r0, 0xA0010000;
CHECKREG r1, 0xA0018000;
CHECKREG r2, 0xA0028000;
CHECKREG r3, 0xA0038000;
CHECKREG r4, 0xA0040000;
CHECKREG r5, 0xA0058000;
CHECKREG r6, 0xA0060000;
CHECKREG r7, 0xA0078000;

imm32 r0, 0xc0010001;
imm32 r1, 0xc0010001;
imm32 r2, 0xc0020002;
imm32 r3, 0xc0030010;
imm32 r4, 0xc0040004;
imm32 r5, 0xc0050005;
imm32 r6, 0xc0060006;
imm32 r7, 0xc0070007;
R3.L = R0.H << 14;
R4.L = R1.H << 14;
R5.L = R2.H << 14;
R6.L = R3.H << 14;
R7.L = R4.H << 14;
R0.L = R5.H << 14;
R1.L = R6.H << 14;
R2.L = R7.H << 14;
CHECKREG r0, 0xC0014000;
CHECKREG r1, 0xC0018000;
CHECKREG r2, 0xC002C000;
CHECKREG r3, 0xC0034000;
CHECKREG r4, 0xC0044000;
CHECKREG r5, 0xC0058000;
CHECKREG r6, 0xC006C000;
CHECKREG r7, 0xC0070000;

// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = R0.L << 12;
R1.H = R1.L << 12;
R2.H = R2.L << 13;
R3.H = R3.L << 14;
R4.H = R4.L << 15;
R5.H = R5.L << 14;
R6.H = R6.L << 7;
R7.H = R7.L << 8;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x10000001;
CHECKREG r2, 0x40000002;
CHECKREG r3, 0xC0000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x40000005;
CHECKREG r6, 0x03000006;
CHECKREG r7, 0x07000007;

imm32 r0, 0x0000d001;
imm32 r1, 0x00000001;
imm32 r2, 0x0000d002;
imm32 r3, 0x0000d003;
imm32 r4, 0x0000d004;
imm32 r5, 0x0000d005;
imm32 r6, 0x0000d006;
imm32 r7, 0x0000d007;
R1.H = R0.L << 3;
R2.H = R1.L << 4;
R3.H = R2.L << 5;
R4.H = R3.L << 6;
R5.H = R4.L << 7;
R6.H = R5.L << 8;
R7.H = R6.L << 9;
R0.H = R7.L << 8;
CHECKREG r1, 0x80080001;
CHECKREG r2, 0x0010D002;
CHECKREG r3, 0x0040D003;
CHECKREG r4, 0x00C0D004;
CHECKREG r5, 0x0200D005;
CHECKREG r6, 0x0500D006;
CHECKREG r7, 0x0C00D007;
CHECKREG r0, 0x0700D001;


imm32 r0, 0x0000e001;
imm32 r1, 0x0000e001;
imm32 r2, 0x0000000f;
imm32 r3, 0x0000e003;
imm32 r4, 0x0000e004;
imm32 r5, 0x0000e005;
imm32 r6, 0x0000e006;
imm32 r7, 0x0000e007;
R2.H = R0.L << 15;
R3.H = R1.L << 15;
R4.H = R2.L << 15;
R5.H = R3.L << 15;
R6.H = R4.L << 15;
R7.H = R5.L << 15;
R0.H = R6.L << 15;
R1.H = R7.L << 15;
CHECKREG r0, 0x0000E001;
CHECKREG r1, 0x8000E001;
CHECKREG r2, 0x8000000F;
CHECKREG r3, 0x8000E003;
CHECKREG r4, 0x8000E004;
CHECKREG r5, 0x8000E005;
CHECKREG r6, 0x0000E006;
CHECKREG r7, 0x8000E007;

imm32 r0, 0x0000f001;
imm32 r1, 0x0000f001;
imm32 r2, 0x0000f002;
imm32 r3, 0x00000010;
imm32 r4, 0x0000f004;
imm32 r5, 0x0000f005;
imm32 r6, 0x0000f006;
imm32 r7, 0x0000f007;
R3.H = R0.L << 13;
R4.H = R1.L << 13;
R5.H = R2.L << 13;
R6.H = R3.L << 13;
R7.H = R4.L << 13;
R0.H = R5.L << 13;
R1.H = R6.L << 13;
R2.H = R7.L << 13;
// RHx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.H = R0.H << 0;
R1.H = R1.H << 0;
R2.H = R2.H << 0;
R3.H = R3.H << 0;
R4.H = R4.H << 0;
R5.H = R5.H << 0;
R6.H = R6.H << 0;
R7.H = R7.H << 0;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010000;
CHECKREG r2, 0x00020000;
CHECKREG r3, 0x00030000;
CHECKREG r4, 0x00040000;
CHECKREG r5, 0x00050000;
CHECKREG r6, 0x00060000;
CHECKREG r7, 0x00070000;

imm32 r0, 0xa0010000;
imm32 r1, 0x00010001;
imm32 r2, 0xa0020000;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xa0050000;
imm32 r6, 0xa0060000;
imm32 r7, 0xa0070000;
R1.H = R0.H << 1;
R2.H = R1.H << 1;
R3.H = R2.H << 1;
R4.H = R3.H << 1;
R5.H = R4.H << 1;
R6.H = R5.H << 1;
R7.H = R6.H << 1;
R0.H = R7.H << 1;
CHECKREG r1, 0x40020001;
CHECKREG r2, 0x80040000;
CHECKREG r3, 0x00080000;
CHECKREG r4, 0x00100000;
CHECKREG r5, 0x00200000;
CHECKREG r6, 0x00400000;
CHECKREG r7, 0x00800000;
CHECKREG r0, 0x01000000;


imm32 r0, 0xb0010000;
imm32 r1, 0xb0010000;
imm32 r2, 0xb002000f;
imm32 r3, 0xb0030000;
imm32 r4, 0xb0040000;
imm32 r5, 0xb0050000;
imm32 r6, 0xb0060000;
imm32 r7, 0xb0070000;
R2.H = R0.H << 15;
R3.H = R1.H << 15;
R4.H = R2.H << 15;
R5.H = R3.H << 15;
R6.H = R4.H << 15;
R7.H = R5.H << 15;
R0.H = R6.H << 15;
R1.H = R7.H << 15;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x8000000F;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;

imm32 r0, 0xd0010000;
imm32 r1, 0xd0010000;
imm32 r2, 0xd0020000;
imm32 r3, 0xd0030010;
imm32 r4, 0xd0040000;
imm32 r5, 0xd0050000;
imm32 r6, 0xd0060000;
imm32 r7, 0xd0070000;
R6.H = R0.H << 12;
R7.H = R1.H << 12;
R0.H = R2.H << 12;
R1.H = R3.H << 12;
R2.H = R4.H << 12;
R3.H = R5.H << 12;
R4.H = R6.H << 12;
R5.H = R7.H << 12;
CHECKREG r0, 0x20000000;
CHECKREG r1, 0x30000000;
CHECKREG r2, 0x40000000;
CHECKREG r3, 0x50000010;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x10000000;
CHECKREG r7, 0x10000000;

pass
